$$ t_{\textrm{smp-pulse}}= \begin{cases} N_{1,\textrm{c}}t_{\textrm{s}}&(\textrm{for } N_1\ge2)\\ \displaystyle\frac{1}2t_{\textrm{s}}&(\textrm{for } N_1=1) \end{cases} $$

$$ t_{\textrm{h,i}}=N_1N_2t_s-2t_{\textrm{smp-pulse}} $$

$$ t_{\textrm{h,i}}= \begin{cases} (N1N2-2N_{1,\textrm{c}})t_{\textrm{s}}&(\textrm{for } N_1\ge2)\\ (N1N2-1)t_{\textrm{s}}&(\textrm{for } N_1=1) \end{cases} $$

$$ t_{\textrm{h,i}}= \begin{cases} (N1-N_{1,\textrm{c}})t_{\textrm{s}}&(\textrm{for } N_1\ge2)\\ \displaystyle\frac{1}{2}t_{\textrm{s}}&(\textrm{for } N_1=1) \end{cases} $$

$$ \frac{V_\textrm{2,d}}{V_\textrm{i}}=\frac{1}{(1+sR_2C_2)(1+sR_0C_0)+sR_0C_2} $$

$$ t_{\textrm{h,d}}=N_1t_s-t_{\textrm{smp-pulse}} $$

  1. ppt : 4 학년 2학기 adc 쪽에 있음.

  2. 논문

    Abstract

    [Implementation: 2 highly interleaved analog-to-digital converters(ADCs)]

    Section 2 : High-Speed, Low-Power ADCs: fundamental ADC limits & Design Tradeoffs

    A. Interleaved ADCs Requirements (High-speed)

    B. Noise and Distortion Budget of an ADC

    (1) SNDR(signal-to-noise and distortion ratio): A(amplitude of input signal), $V_{i,pp-diff}$(maximum peak-peak differential input voltage), N(resolution of ADCs), $\sigma_{DNL}$ & $\sigma_{INL}$(standard deviation of DNL and INL in LSBs), $f_in$(input frequency), $\sigma_j$(std of timing jitter in seconds), $\sigma_n$(std of thermal noise in ADCs) ⇒effects from time interleaving 은 (1)식에 포함 X

    $$ SNDR_{tot}= 10\log{\frac{\frac{1}{2}A^2}{\frac{V^2_{i,pp-diff}}{2^{2N}}(\frac{1}{12}+\frac{1}{4}{\sigma_{DNL}^2}+\sigma_{DNL}^2)+(\sqrt2\pi f_{in}A\sigma_j)^2+\sigma_n^2}} $$

    (2) SNDR limit from jitter

    $$ SNDR_{jitter}=-20\log(2\pi f_{in}\sigma_j) $$

    Section 3 : Voltage-based time-interleaving architectures for high-speed ADCs (+resolution high 여도 ok )

    A. Voltage-Based Interleaver Architectures

    Fig. 1. Direct sampling with buffered subsampling [2] . Waveforms are shown for 50% duty cycle clocking

    Untitled

    1. provide shortest path from input to sampling CAP with minimum resistance
    2. 1개 이상 sampling switch 가 동시에 closed
    3. 1개의 sampling switch만 close 되면 highest bandwidth but shortest sampling pulsed required
    4. 너무 많은 스위치 달리면 Vi 에 input capacitance 증가
    5. sampled voltage 는 Cs에 보관되고 forwared through a buffer and demux structure to sampling capacitor of sub-ADC $C_{s,ADC}$

    Fig. 2. Inline demux sampling with buffered subsampling [4] .

    Untitled

    1. stack 2 switches to reduce the number of parallel switches at the input
    2. 닫히는 순서: lnline demux switch ⇒ Sampling switch
    3. 열리는 순서 : Sampling switch ⇒ lnline demux switch
    4. 결국 sampling time 은 오직 sampling switch clock 의 falling edge에만 영향
    5. Inline demux switch : timing critical clock signal 의 수를 현저히 감소

    B. Interleaver Model

    C. Inline Demux Sampling Model

     ![kull4-2519397-small.gif](<https://s3-us-west-2.amazonaws.com/secure.notion-static.com/38addfa0-7716-4c92-9810-86fe19193985/kull4-2519397-small.gif>)
    

    Fig. 4.

    Inline demux interleaver (Fig. 2) with simplified switch model of Fig. 3. 아까 figure 2에서 inline demux sampling(앞쪽 회색 block에) fig3의 스위치 모델 집어 넣은 버전

    Fig. 5.

    RC equivalent of the inline demux interleaver from Fig. 4.

    Section 4 : Implementation and measurement results of high-speed CMOS ADC at 90 GS/s & 8 bit resolution(667 mW power consumption) + low-power implementation at 36 GS/s & 6 bit resolution(100 mW power consumption)