$$ t_{\textrm{smp-pulse}}= \begin{cases} N_{1,\textrm{c}}t_{\textrm{s}}&(\textrm{for } N_1\ge2)\\ \displaystyle\frac{1}2t_{\textrm{s}}&(\textrm{for } N_1=1) \end{cases} $$
$$ t_{\textrm{h,i}}=N_1N_2t_s-2t_{\textrm{smp-pulse}} $$
$$ t_{\textrm{h,i}}= \begin{cases} (N1N2-2N_{1,\textrm{c}})t_{\textrm{s}}&(\textrm{for } N_1\ge2)\\ (N1N2-1)t_{\textrm{s}}&(\textrm{for } N_1=1) \end{cases} $$
$$ t_{\textrm{h,i}}= \begin{cases} (N1-N_{1,\textrm{c}})t_{\textrm{s}}&(\textrm{for } N_1\ge2)\\ \displaystyle\frac{1}{2}t_{\textrm{s}}&(\textrm{for } N_1=1) \end{cases} $$
$$ \frac{V_\textrm{2,d}}{V_\textrm{i}}=\frac{1}{(1+sR_2C_2)(1+sR_0C_0)+sR_0C_2} $$
$$ t_{\textrm{h,d}}=N_1t_s-t_{\textrm{smp-pulse}} $$
ppt : 4 학년 2학기 adc 쪽에 있음.
Abstract
[Implementation: 2 highly interleaved analog-to-digital converters(ADCs)]
필요성 : communication require faster converters + CMOS 공정이 더 이상 significant speed advantages X , emerging wired communication standard 는 ADCs 에 build 됨. 점점 더 same band 에서 data rate 를 올려서 higher-order modulation 을 할 것이다. 즉 ADCs with at least 8 bit resolution at high sampling rate 가 지속적으로 성장할 것이다.
그래서 8 bit 이상 resolution 을 위해 뭐가 효율적이냐 : SAR ADCs ⇒장점: flexible architecture, power efficiency, suitability for digital CMOS process. 즉, low total number of comparisons to determine the digital output + absence of amplification during conversion(amp 는 pipelined ADCs의 특징, amp의 부재로 인해 low supply voltage 에서 converter가 동작)단점: slower clock rate.
Time-interleaved front end sampler + SAR ADCs ⇒ High speed converter ⇒ TI- ADCs 디자인은 divide-and-conquer approach 채택(power and area 가 sub-ADC에 의해 결정됨. speed & bandwidth & interleaving accuracy 는 front end interleaver(-analog input signal demultiplexing structure 이며 sampling stage + buffter 로 구성)에 의해 결정)
ADCs architecture | 6bit | 8bit |
---|---|---|
input bandwidth | > 20GHz | > 20GHz |
inline demux sampling | 32X interleaving | 64X interleaving |
sampling rate | 36GS/s at 110mW | 90GS/s at 667mW |
SNDR | above 31.6 dB at 36 GHz(Nyquist) | above 36 dB up to 6.1 GHz, above 33 dB up to 19.9 GHz |
Area | $0.048 mm^2$ | $0.45 mm^2$ |
Section 2 : High-Speed, Low-Power ADCs: fundamental ADC limits & Design Tradeoffs
A. Interleaved ADCs Requirements (High-speed)
enables the separation of ADC requriements (Interleaver 용 // sub-ADCs 용)
→ 둘 다 total noise budget 에 기여(ADC 가 higher speed & precision requirement 일수록, interleaver 에 더 많은 noise budget 이 할당되어야 함-interleaver 가 technology constraint 에 의해 더 강하게 bound 됨)
→ skew and BW mismatch 는 오직 first sampling stage 에만 영향을 주고, gain mismatch and offset 은 sub-ADCs 에도 영향을 줄 수 있음(차이 확인!)
B. Noise and Distortion Budget of an ADC
(1) SNDR(signal-to-noise and distortion ratio): A(amplitude of input signal), $V_{i,pp-diff}$(maximum peak-peak differential input voltage), N(resolution of ADCs), $\sigma_{DNL}$ & $\sigma_{INL}$(standard deviation of DNL and INL in LSBs), $f_in$(input frequency), $\sigma_j$(std of timing jitter in seconds), $\sigma_n$(std of thermal noise in ADCs) ⇒effects from time interleaving 은 (1)식에 포함 X
$$ SNDR_{tot}= 10\log{\frac{\frac{1}{2}A^2}{\frac{V^2_{i,pp-diff}}{2^{2N}}(\frac{1}{12}+\frac{1}{4}{\sigma_{DNL}^2}+\sigma_{DNL}^2)+(\sqrt2\pi f_{in}A\sigma_j)^2+\sigma_n^2}} $$
(2) SNDR limit from jitter
$$ SNDR_{jitter}=-20\log(2\pi f_{in}\sigma_j) $$
Section 3 : Voltage-based time-interleaving architectures for high-speed ADCs (+resolution high 여도 ok )
A. Voltage-Based Interleaver Architectures
direct sampling & inline demux sampling 으로 catagorize⇒ 둘 다 implement subsampling for larger interleaving ratio
Direct Sampling:
Fig. 1. Direct sampling with buffered subsampling [2] . Waveforms are shown for 50% duty cycle clocking
Fig. 2. Inline demux sampling with buffered subsampling [4] .
B. Interleaver Model
Fig. 3. Simplified switch model
total gate capacitance (= drain cap + source cap + bulk cap)
on-resistance of the switch
drain cap 과 source cap은 constant(independant of gate voltage)라 가정하고, leakage from sampling cap in switch-off state 는 없다 가정
transition frequency 는 gate cap과 on-resistance of the switch 로 표현 가능
effective transition frequency = p* transition frequency
p = correction factor = $\frac{ due\ to\ wiring\ of\ a\ sampling\ switch}{due\ to\ without\ wiring\ of\ a\ sampling\ switch} of\ parasitic\ capacitance\ + R_{on}$ = or by simulating the transfer function of inter leaver and fitting p
(동일한 기술로 만든 difference interleaver는 p 거의 동일)
C. Inline Demux Sampling Model
![kull4-2519397-small.gif](<https://s3-us-west-2.amazonaws.com/secure.notion-static.com/38addfa0-7716-4c92-9810-86fe19193985/kull4-2519397-small.gif>)
Fig. 4.
Inline demux interleaver (Fig. 2) with simplified switch model of Fig. 3. 아까 figure 2에서 inline demux sampling(앞쪽 회색 block에) fig3의 스위치 모델 집어 넣은 버전
sampling cap 식(1), Cs(total sampling cap)가 defince the kT/C noise limit of converter
$R_i$= input resistance to the interleaver
inline demux switch 왜쓰는지 아이패드 fig4 그림에 적어놨음
fig4는 fig5로 simplify됨
Fig. 5.
RC equivalent of the inline demux interleaver from Fig. 4.
Section 4 : Implementation and measurement results of high-speed CMOS ADC at 90 GS/s & 8 bit resolution(667 mW power consumption) + low-power implementation at 36 GS/s & 6 bit resolution(100 mW power consumption)